Job Description / Skills Required
8 to 12 years of static timing analysis and constraints generation.
Hands-on experience in full-chip/block-level Static Timing Analysis, timing constraints generation and timing convergence.
Knowledge in physical design for implementation/generation of timing ECOs is required.
Experience in DFT timing closure for various modes e.g. scan shift and capture, transition faults, MBIST.
Familiar with several clocking implementation strategies and their analysis from a timing perspective.
Expertise in analyzing and converging crosstalk delay and noise glitch.
Understanding of process variation effect modeling and experience in design convergence taking into account variations required.
Expert with Synopsys Prime-Time and excellent scripting skills with Python, Perl, Tcl, Make, etc.
Skilled in methodology and/or flow development.
Minimum of BS Electrical/Computer engineering (MS preferred).