Senior Chip level RTL integration Engineer

Job Description / Skills Required

10+ years of the ASIC design flow, FE and Design verification, Synthesis, Logic Equivalence, Lint, scripting and netlist generation.
RTL design, IP integration and timing closure on large complex designs.
Logic synthesis with DFT insertion.
ASIC design flow and netlist flow checks – CDC, Logical Equivalence.
Design interfacing to PD for floorplanning and timing closure.
Strong communication skills are a must as the candidate will interface across several disciplines within the company.
Familiarity with DFT and backend related methodology and tools is a plus.
Own all aspects of development design for chiplevel:
Chiplevel clocking and reset design.
Internal and external IP integration.
Design of chiplevel logic for connectivity of IP blocks to main ASIC infrastructure.
Ownership of the Integration Spec for the design project.
Data and environment management.
Optimization and integration of memories and hard macros.
Work closely with Chip Architecture, Design verification, Physical Design, DFT, and power teams to achieve first tapeout success.
Minimum of BS Electrical/Computer engineering (MS preferred).