Job Description / Skills Required
Location – San Francisco Bay Area (Saratoga/San Jose), California
Develop a scalable SoC verification infrastructure, spanning block level to full chip level, and ASIC to FPGA.
Develop and implement test plans, close coverage for functional sign-off, working with design and systems engineers.
Support for silicon bringup and production as needed.
Experience with functional verification, constrained random methodologies such as UVM/OVM/SV, assertions, coverage techniques, UPF.
Experience with running and debugging gate level simulations.
Familiar with wireless communication protocols, CPU/memory subsystems, bus interfaces
Skilled in scripting, automation, enabling high productivity
Desire to work in a fast paced startup environment
MS in Electrical Engineering or related field with 4+ years of ASIC design verification experience
Two or more SoC design cycles with significant DV roles
Verification of low power designs that include power islands. sleep/standby, wake/active states.