Avicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)
Responsibilities:
- Develop micro architecture for the digital section of the ASIC.
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Write RTL in verilog for the blocks and simulate them.
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Supervise the verification team and ensure they have sufficient coverage.
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Develop SDC files for the backend.
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Interact with the backend engineers to make sure the design meets all requirements such as STA, IR, etc.
Qualifications:
- MS or PhD in Electrical Engineering.
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10 years of experience in digital design from specs to architecture, design, bench testing and all the way to high volume production.
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Deep understanding of RTL design for high speed datapath and signal processing, experience with different bus architectures, MCU integration.
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Knowledge of the backend flow and ability to check STA reports and resolve any issues that require RTL change.
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Ability to supervise the verification effort.
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3+ years of Management experience.