Senior ASIC Digital Design Manager

Sunnyvale, CA, US

Job Description / Skills Required

Avicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications.  This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products.  (www.avicena.tech)   

Responsibilities:

  • Develop micro architecture for the digital section of the ASIC. 
  • Write RTL in verilog for the blocks and simulate them. 
  • Supervise the verification team and ensure they have sufficient coverage. 
  • Develop SDC files for the backend. 
  • Interact with the backend engineers to make sure the design meets all requirements such as STA, IR, etc. 
 
Qualifications:
  • MS or PhD in Electrical Engineering. 
  • 10 years of experience in digital design from specs to architecture, design, bench testing and all the way to high volume production. 
  • Deep understanding of RTL design for high speed datapath and signal processing, experience with different bus architectures, MCU integration. 
  • Knowledge of the backend flow and ability to check STA reports and resolve any issues that require RTL change. 
  • Ability to supervise the verification effort. 
  • 3+ years of Management experience.